1. Field of the Invention
The present disclosure relates to semiconductor processing. More particularly, the present disclosure relates to a method for providing an oxide layer at predetermined locations on a substrate, e.g. on a three-dimensional structure in a substrate, for example a three-dimensional structure having a high aspect ratio, for example an aspect ratio (width over height ratio) below about 5.
2. Description of the Related Technology
Silicon oxide is a know material to be used in semiconductor process technology. Several techniques exist to deposit or grow silicon oxide. Silicon oxide may be formed by thermal oxidation of silicon. Alternatively, chemical vapor deposition (CVD) may be used to form silicon oxide. By using this process, silicon oxide is formed by a chemical reaction in a process chamber at temperatures typically ranging from 200° C. to 500° C. For this purpose specific precursors such as e.g. silane (SiH4), TEOS (Tetraethyl Orthosilicate —Si(OC2H5)4) or HMDSO (hexamethyldisiloxane) are commonly used.
The quality (electrical and mechanical properties) of the formed oxide mainly depends on the amount of impurities trapped in the oxide during formation, and thus also depends on the technique used to form it. The impurities may, for example, result from incompletely dissociated precursors.
In order to obtain high quality oxide films at low temperature, plasma enhanced chemical vapor deposition (PECVD) may be used to efficiently dissociate the precursors.
Another way of forming silicon oxide is by electrochemical oxidation of silicon, such as anodization.
U.S. Pat. No. 5,736,454 describes a method for forming a silicon dioxide layer on a silicon substrate, e.g. a field oxide layer or the oxide layer of a thin film transistor. The method comprises conducting an electrolytic reaction at room temperature such that a silicon dioxide layer is formed on a silicon substrate acting as an anode, wherein pure water is used as an electrolyte of the electrolytic reaction. In order to obtain this, an aluminum film is evaporated at the backside of the silicon substrate to form the anodic contact for anodization. The method of U.S. Pat. No. 5,736,454 requires assist techniques in order to obtain good quality silicon oxide that can be used as, for example, a gate oxide. Therefore, the formed silicon dioxide layer is further subjected to a rapid thermal densification carried out in an inert gas atmosphere and at a temperature of between 700° C. and 1000° C. for a time period such that the silicon dioxide is densified. It is a disadvantage of the method described in U.S. Pat. No. 5,736,454 that it cannot be applied to thin wafers, which need to be attached to a carrier for handling, which carriers are non-conductive. It is furthermore a disadvantage of the method described in U.S. Pat. No. 5,736,454 that it is a slow process: 50 Å to 88 Å of oxide are formed in between 20 and 100 minutes.
PECVD deposition is typically performed at temperatures between 200° C. and 400° C. For advanced packaging applications, which covers 3D integration of IC and packages, typical deposition temperatures need to remain below 200°, preferably below 100° C. for example to allow processing on carrier wafers, that are typically glued with polymer based materials that cannot withstand these high temperatures. With PECVD, it is possible to deposit layers at temperatures below 200° C., often down to 80° C., but the oxide deposited at these temperatures exhibit poor properties, for example poor mechanical properties. The layers suffer from low breakdown field and pinholes. Also the conformity of the deposited layers is poor, i.e. the thickness of the deposited layer is not homogenous in deep 3D structures.
Oxidation of silicon appears to be a difficult process that may require post-treatment, additional assist techniques or specific substrate preparation in order to form good quality oxide. A good quality oxide for example has a parasitic leakage current below 100 nA/cm2.
Furthermore, when a via structure is formed on a substrate, it may be difficult to provide an oxide inside these via structures because of lithographic limitations which are due to small depth of focus of scanners used for performing patterning and/or reflective effects.